1. Field of the Invention
The invention relates to a storage unit, and more particularly to a radiation-hardened storage unit.
2. Description of the Related Art
In aerospace electronic systems, the memory is a very important part occupying most of the chip area. In the space environment, an electronic system may be adversely affected by radiations from the galaxy, the sun, the earth and other radiators. Therefore, the memory is one of the most vulnerable parts in an aerospace electronic system for its high density.
Total ionizing dose radiation, single event latchup, and single event upset are three effects that most significantly affect the memory. In the 0.18 um process and advanced processes, as a thickness of the gate oxide is less than 5 nm, main effect of the total ionizing dose radiation is leakage current generated in a NMOS transistor. The single event latchup is that instantaneous current pulses generated by single event radiation are cyclically amplified by a feedback loop parasitized in an integrated circuit and thus burning a chip therein. The single event upset is that instantaneous current pulses generated by single event radiation at sensitive nodes lead to data error in a storage unit.
As shown in FIGS. 1 and 2, in order to harden total ionizing dose radiation of a storage unit, a profiled gate is used for hardening a NMOS transistor. In FIG. 1, an annular FET layout technique is used for hardening the NMOS transistor: one of a drain 102 and a source 103 is completely surrounded by a gate 101 whereby physically isolating a path generated by leakage current and hardening total ionizing dose radiation. In FIG. 2, a horseshoe FET layout technique is used for hardening the NMOS transistor: one of a drain 202 and a source 203 is half surrounded by a gate 201 whereby increasing a path length of leakage current, reducing leakage caused by total ionizing dose radiation, and hardening total ionizing dose radiation.
Currently, to harden single event latchup of a storage unit, an isolating ring is added between a NMOS transistor layout and a PMOS transistor layout, so that a loop gain of a parasitized feedback ring is far less than 1, and instant current of single event radiation is not to be amplified.
Conventional methods for hardening single event upset include: a triple modular redundancy (TMR), a dual interlocked storage cell (DICE) in FIG. 3, and a heavy ion tolerant (HIT) unit in FIG. 4. In FIG. 3, each of four storage nodes X1, X2, X3 and X4 in a DICE unit 300 is controlled by an inverter via two adjacent nodes, and thus hardening single event upset via dual-node feedback. In FIG. 4, a HIT unit 400 makes use of different drive capability of transistors 407, 408, 411 and 412 (namely drive capability of transistors with a greater aspect ratio is better than that with a smaller aspect ratio) to recover upset nodes, whereby hardening single event upset.
Conventional methods for hardening single event upset of a storage unit may increase an area thereof by 140% to 200%, and those for hardening total ionizing dose radiation and single event latchup of the storage unit may increase an area thereof by 200%, which may result in substantial increase in areas of the storage unit and the memory, and make it impossible to facilitate a small-size integrated circuit.